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An Efficient Regular Matrix Inversion Circuit Architecture for MIMO Processing A novel circuit architecture and algorithm is presented for the efficient implementation of a matrix inversion unit. The division-free algorithm yields a scaled version of the inverse and the scaling factor. Based on the Sherman-Morrison formula, the proposed architecture is characterized by regular, locally-connected arrays of processing units and simple iterative processing. It is especially well-suited for covariance matrices, or any other matrix which can be constructed from rank-one updates of an initial matrix whose inverse is known. While it constitutes an ideal solution for antenna array MMSE (minimum mean-square error) processing, it can also be generalized to many other applications with little effort. Implementation results of a heavily pipelined matrix inverter on a Xilinx Virtex-II FPGA are presented, including cost in logic slices and maximum clock frequency. The cost / complexity of the proposed solution is comparable to, and in many cases better than, known alternatives. Isabelle LaRoche et Sébastien Roy mai 2006, Proceedings of the IEEE International Symposium on Circuits and Systems, 2006. , Kos, Greece, Anglais, Bibtex: @conference{, author = {Isabelle LaRoche and Sébastien Roy}, title = {An Efficient Regular Matrix Inversion Circuit Architecture for MIMO Processing}, journal = {Proceedings of the IEEE International Symposium on Circuits and Systems, 2006. }, year = {2006}, month = {May}, language = {Anglais}, } Dernière modification le jeudi 23 novembre 2006 à 13h57 par Isabelle LaRoche |