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|Tous|Domaines|Projets Spéciaux|Auteurs|Thèses et Mémoires| Highly-parallel decoding architectures for convolutional turbo codes Highly parallel decoders for convolutional turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleavers. To solve the memory conflict problem of extrinsic information in a parallel decoder, a block-like approach in which data is written row-by-row and READ diagonal-wise is proposed for designing collision-free parallel interleavers. Furthermore, a warm-up-free parallel sliding window architecture is proposed for long turbo codes to maximize the decoding speeds of parallel decoders. The proposed architecture increases decoding speed by 6%–34% at a cost of a storage increase of 1% for an eight-parallel decoder. For short turbo codes (e.g., length of 512 bits), a warm-up-free parallel window architecture is proposed to double the speed at the cost of a hardware increase of 12%. Zhi Yong He, Paul Fortier et Sébastien Roy octobre 2006, IEEE Trans. VLSI Systems, , anglais, Bibtex: @article{, author = {Zhi Yong He and Paul Fortier and Sébastien Roy}, title = {Highly-parallel decoding architectures for convolutional turbo codes}, journal = {IEEE Trans. VLSI Systems}, year = {2006}, month = {October}, language = {anglais}, } Dernière modification le jeudi 26 août 2010 à 10h49 par Sébastien Roy